1. Field of the Invention
The present invention relates to boosted-voltage drive circuits which drive a voltage boosted as compared to an external power supply voltage, and semiconductor devices employing the same.
2. Description of the Background Art
In semiconductor integrated circuit devices, e.g. semiconductor memory devices, a power supply voltage lower than an external power supply voltage Vdd can be generated on chip and supplied as an internal power supply voltage Vcc to ensure reliability and the like. In semiconductor devices, dynamic random access memories (DRAMs) in particular, however, a voltage boosted as compared to an external power supply potential can be generated on chip as a potential to drive a word line for selecting a memory cell.
FIG. 28 is a schematic block diagram showing a configuration of a memory array in a conventional DRAM.
A memory array MA is divided into blocks or a plurality of memory sub arrays SMA1 to SMAn. Sense amplifier bands SAB1 to SABn-1 have any sense amplifier band SABj shared e.g. by adjacent memory sub arrays SMAj and SMAj+1. Furthermore, sense amplifier bands SAB0 and SABn are provided outside memory sub arrays SMA1 and SMAn, respectively.
Memory sub arrays SMA1 to SMAn are provided with block row decoders BRD1 to BRDn, respectively. Sense amplifier bands SAB1 to SABn-1 are provided with sense amplifier control circuits SAC0 to SACn, respectively.
There are also provided word line drivers WD1 to WDn which respond to a signal decoded by block row decoders BRD1 to BRDn to drive the potential level of the corresponding word line to an active level (potential Vpp).
For example, when memory sub array SMA1 is selected in response to an externally applied row address signal, word line driver WD1 powered with a boosted voltage starts to operate according to a result obtained from the address signal decoded by block row decoder BRD1 and drives a selected word line in memory sub array SMA1 to the potential Vpp level.
The data read from a memory cell thus selected is amplified by a sense amplifier of sense amplifier band SAB1 via a bit line. When the read cycle completes, word line driver WD1 again operates to decrease the potential level of the word line from the potential Vpp level to a ground potential level (GND level).
In addition, for example, a bit-line isolation signal line is provided to control a block select transistor for providing isolation of a bit line between memory sub array SAB1 and sense amplifier band SAB1. As is similar to a word line, the bit-line isolation signal line transmits a signal which is driven to attain potential level Vpp.
In a standby state the bit-line isolation signal line is held at potential level Vpp so as to prevent drop of the voltage corresponding to the threshold voltage of the block select transistor. When a read cycle is started, before the potential level of a word line initially rises to a selected, potential level (Vpp) the bit-line isolation signal line for selectively providing isolation of a bit line between non-selected memory sub array SMA1 and sense amplifier band SAB1 falls from potential level Vpp to the GND level. When the read cycle completes, the bit-line isolation signal line for the non-selected memory sub array SMA1 again rises to potential level Vpp.
FIG. 29 is a circuit diagram for illustrating a configuration of sense amplifier band SAB1 shown in FIG. 28.
Sense amplifier band SAB1 includes a sense amplifier SA including an n-channel transistor amplifier configured of n-channel MOS transistors N10 and N12 and p-channel transistor amplifier configured of p-channel MOS transistors P10 and P12, and block select gate BSG1 responsive to a signal 1SO1 for selectively opening and closing a connection between sense amplifier SA and a pair of bit lines BL1,/BL1 in memory sub array SMA1.
BSG1 includes an n-channel MOS transistor N20 having its gate potential driven by a bit-line isolation signal line ISO1 for opening and closing a connection of bit line BL1 to one input node of sense amplifier SA, and n-channel MOS transistor N22 having its gate potential driven by signal ISO1 transmitted on bit-line isolation signal line ISO1 for selectively opening and closing a connection of bit line/BL1 to the other input node of sense amplifier SA.
Sense amplifier band SAB1 also includes a block select gate BSG2 which selectively opens and closes a connection between a pair of bit lines BL2,/BL2 in memory sub array SMA2 and sense amplifier SA. Block select gate BSG2 includes an n-channel MOS transistor N24 having its gate potential driven by a bit-line isolation signal line ISO2 for selectively opening and closing a connection between bit line BL2 and one input node of sense amplifier SA, and an n-channel MOS transistor N26 having its gate potential driven by signal line ISO2 for selectively opening and closing a connection between bit line/BL2 and the other input node of sense amplifier SA.
Sense amplifier band SAB1 also includes a select gate SG opening and closing a connection between an associated I/O line pair and an associated bit line pair in response to a column select signal YL from a column decoder CLD, and a precharge circuit PCC responsive to a precharge signal RP for precharging an associated bit line pair to attain a precharge potential Vcc/2 corresponding to half the potential level of internal power supply potential Vcc.
As described above, bit-line isolation signal lines ISO1 and ISO2 are also driven to the level of boosted potential Vpp.
FIG. 30 is a circuit diagram illustrating a configuration of a first conventional level shifter circuit 9000 for converting a signal having the logical amplitude of the internal power supply potential Vcc level to that having the logical amplitude of the boosted voltage Vpp level in a circuit block powered with boosted voltage Vpp as described above.
Level shifter circuit 9000 includes p-channel MOS transistors P30 and P32 having their respective sources receiving power supply potential Vpp and their respective gates and drains cross-coupled with each other, and n-channel MOS transistors N30 and N32 respectively connected between the drains of p-channel MOS transistors P30 and P32 and ground potential GND.
The gate of n-channel MOS transistor N30 is driven by an input signal IN having the logical amplitude of internal power supply voltage Vcc. The gate of n-channel MOS transistor N32 is driven by a signal output from an inverter INV1 driven by power supply potential Vcc and receiving and inverting signal IN for output.
FIG. 31 is a timing chart for representing an operation of level shifter circuit 9000 shown in FIG. 30.
At time t1, input signal IN rises from ground potential GND to internal power supply potential Vcc and responsively transistor N30 is turned on and the gate potential of p-channel MOS transistor P32 rises to ground potential GND. Responsively transistor P32 is turned on, while the output from inverter INV1 attains the GND level and responsively a signal OUT rises to boosted potential Vpp at time t2, since n-channel MOS transistor N32 has been turned off.
At time t3, input signal IN falls to ground potential GND and responsively transistor N30 is turned off and transistor N32 is turned on. Since transistor P30 turned off allows the gate of transistor P32 to be charged to attains potential level Vpp, transistor P32 is turned off and transistor N32 turned on thus allows output signal OUT to fall to ground potential GND at time t4.
FIG. 32 is a circuit diagram for illustrating a configuration of a second conventional level shifter circuit 9200.
Level shifter circuit 9200 differs in configuration from level shifter circuit 9000, as described below.
That is, transistor N30 is replaced by a transistor N40 receiving power supply potential Vcc at its gate and input signal IN at its source, and transistor N32 is replaced by an n-channel MOS transistor N42 receiving input signal IN at its gate and connected between the source of transistor P32 and ground potential GND.
FIG. 33 is a timing chart for representing an operation of level shifter circuit 9200 shown in FIG. 32.
At time t1, input signal IN rises from potential level Vcc to ground potential GND and responsively transistor N40 is turned on and the gate potential level of transistor P32 drops to the ground potential. Since transistor N42 is turned off, output signal OUT rises to power supply potential Vpp.
At time t2, input signal IN rises from potential level GND to power supply potential Vcc and responsively transistor N40 is turned off and transistor N42 is turned on. Responsively, transistor N42 allows the output node to discharge and signal OUT falls from potential Vpp to ground potential GND.
FIG. 34 is a circuit diagram for illustrating a configuration of a third conventional level shifter circuit 9400.
Level shifter circuit 9400 includes p- and n-channel MOS transistors P48 and N52 connected in series between power supply potential Vpp and ground potential GND, and a p-channel MOS transistor P50 connected between power supply potential Vpp and a connection point between transistors P48 and N52.
The gate of p-channel MOS transistor P48 receives a signal PR changing in the amplitude of voltage Vpp, and the gate of transistor N52 receives signal IN changing in the amplitude of voltage Vcc.
Level shifter circuit 9400 also includes a p-channel MOS transistor P52 and an n-channel MOS transistor N54 operating as an inverter connected between power supply potential Vpp and ground potential GND.
An input node of inverter 9402 configured of transistor P52 and N54 is connected to a connection node of transistors P48 and N52. The gate of transistor P50 is connected to an output node of inverter 9402.
FIG. 35 is a timing chart for representing an operation of level shifter circuit 9400.
At time t1, signal PR rises from potential level GND to potential level Vpp. Responsively, transistor P48, which has been turned on prior to time t1, is turned off. At time t2, signal IN rises from ground potential GND to potential Vcc. Thus, transistor N52 is turned on and the input node of inverter 9402 falls to the ground potential. Responsively, at time t3, output signal OUT rises from ground potential GND to potential level Vpp.
At time t4, signal IN falls to ground potential GND. Responsively, transistor N52 is turned off. At time t5, input signal PR falls to ground potential GND. Responsively, transistor P48 is turned on. Thus, the input node of inverter 9402 rises to potential level Vpp and responsively at time t6 output signal OUT falls to ground potential GND.
In general the level shifter as described above allows a signal changing in the amplitude of potential Vcc to be converted to a signal changing in the logical amplitude of boosted potential Vpp.
Meanwhile, as transistors configuring a semiconductor integrated circuit are increasingly microfabricated, an n-channel MOS transistor provided particularly for a circuit block powered by such boosted voltage Vpp and having its drain connected to an output node providing an output changing in the amplitude of boosted voltage Vpp, has its longevity reduced disadvantageously due to hot carrier.
That is, the channel electrons flowing from the source to drain of such an n-channel MOS transistor obtain high energy resulting from a strong electric field in a vicinity of the drain and thus causes collision current at an end of the drain. A portion of the electrons and hot holes generated by the collision current are injected into and captured by a gate oxide film to cause the so-called hot carrier injection. Consequently, the threshold value, conductance and the like of the transistor shifts with time and the circuit eventually fails to operate normally.
The hot carrier injection as described above is maximized when drain and gate voltages are applied to achieve a gate-source voltage VGS of 1/2 Vds, wherein Vds represents the drain-source voltage. Thus, in the inverter as shown in FIG. 36, hot carrier is significantly generated during the logical transition period during which input signal IN crosses the logical threshold value, as shown in FIG. 37. As is disclosed in Journal of Solid-State Circuits Vol. SC-21 (1986) pp. 187-191, it is known that hot carrier generation is greater when an output node having been charged to attain a logical high level discharges and attains ground potential GND.
The disadvantage described above is overcome e.g. by the so-called Normally-On Enhancement Mostet Insertion (NOEMI) technique, i.e. insertion of a normally-on transistor between an output node having the amplitude of boosted voltage Vpp and a pull-down transistor, as described in 1987 Symp. VLSI Circuits Dig. Tech. Papers pp.13-14, for example. FIG. 38 is a circuit diagram showing an exemplary configuration of the NOEMI technique described above for an inverter.
A p-channel MOS transistor P 1 and n-channel MOS transistors N1 and N2 are connected in series between boosted potential Vpp and ground potential GND. N-channel MOS transistor M1 is always turned on, receiving a potential VGG at its gate. Under the conditions, the maximum source-drain voltage Vds applied to n-channel MOS transistor M1 is Vpp-(VGG-Vt) and the maximum source-drain voltage Vds applied to transistor M2 is Vgg-Vt, wherein Vt represents the threshold voltage of transistor M1.
The introduction of transistor M1 can alleviate source-drain voltage Vds applied to each of n-channel MOS transistors M1 and M2 and significantly reduce the generation of hot carrier to overcome the disadvantageously reduced longevity of the transistors described above.
In the NOEMI technique as described above, however, transistors M1 and M2 corresponding to n-channel MOS pull-down transistor are connected in series. Thus, it disadvantageously requires an increased period of time to pull an output node charged to attains to the boosted voltage Vpp level down to the ground potential GND level. In particular, word lines and bit-line isolation signal lines, which have large load capacity, are subject to significant time delay which disadvantageously results in the delay in access time in DRAMs and the like.
Disadvantage of Hierarchical Word-Line Configuration
Word lines in the so-called, hierarchical word-line configuration have the disadvantage described below.
FIG. 39 is a schematic block diagram for illustrating a configuration of a memory cell array mat for the hierarchical word-line configuration.
The memory cell array mat differs in configuration from that described with reference to FIG. 28, as described below.
Initially, in response to an externally applied row address signal, a row predecoder RPD predecodes the row address signal. Responsively a main word driver MVD activates a main word line MWL selected.
In response to the predecoded signal from row predecoder RPD, a subdecoder SDR also activates the potential level of a sub decode line SD corresponding to the selected row address.
A sub word driver SWD provided at an intersection of the selected main word line MWL and the selected sub decoder line SDL allows sub word line SWL to be placed in a selected state.
FIG. 40 is a circuit diagram for illustrating a configuration of subdecoder SDR and main word line MWL and sub word line SWL.
Sub decoder SDR is adapted to respond e.g. to a predecoded signal to activate any of four subdecode lines SD0 to SD3.
For example, when a predecoded signal HIT1 is placed in an active state, signal HIT1 is input to an input node of an inverter configured of a p-channel MOS transistor P80 and an n-channel MOS transistor N80 connected between boosted potential Vpp and ground potential GND. In response to the activation of signal HIT1 (or a transition of signal HIT1 to a low level), a sub decode signal SD1 is placed in an active state (or the potential level Vpp state).
Among the sub word lines connected to a then active main word line MWL (i.e. a word line at boosted potential Vpp) are activated sub word lines SWL10 to SWL1n selected by sub decode line SD1.
For example, sub word line SWL1n is connected to an output node of the inverter configured of p-channel MOS transistor P82 and an n-channel MOS transistor N82 connected between sub word line SD1 and ground potential GND. The inverter configured of transistors P82 and N82 has an input node connected to main word line MWL.
FIG. 41 is a time chart showing the potential level of a node N1, the potential level of signal HIT1, and a substrate current Isub of n-channel MOS transistor N80 that vary with time in the configuration described above, wherein node N1 is a drain node of n-channel MOS transistor N80 which drives sub decode line SD1.
At time t1, signal HIT1 starts to transition to an inactive state or the potential Vpp level. Responsively, n-channel MOS transistor N80 starts to discharge and the potential level of node N1 starts to drop towards ground potential GND, while substrate current Isub having a high peak value flows in n-channel MOS transistor N80.
Similarly, at time t2, signal HIT1 starts to transition from potential level Vpp towards ground potential GND. Responsively, the potential level of node N1 starts to rise from ground potential GND towards potential level Vpp, while substrate current Isub flows in transistor N80.
As described above, such substrate current Isub flowing in transistor N80 means that impact ionization is caused at the drain of transistor N80 and thus degrades the reliability of transistor N80.
Furthermore, for the hierarchical word-line configuration as shown in FIG. 40, sub decoder SDR operates more frequently than a driver which drives main word line MWL, since sub decoder SDR is required to operate when any of main word lines MWL is selected.
In other words, although an n-channel MOS transistor present in main word driver MWD operates in the logical amplitude between boosted potential Vpp and ground potential GND, transistor N80 in sub decoder SDR operates more frequently than the n-channel MOS transistor in main word driver MWD and any degradation of its reliability will be a severe disadvantage.